By John Hu
This ebook will introduce a number of strength administration built-in circuits (IC) layout recommendations to construct destiny energy-efficient “green” electronics. The objective is to accomplish excessive potency, that's necessary to meet shoppers’ turning out to be desire for longer battery lives. the point of interest is to review topologies amiable for complete on-chip implementation (few exterior parts) within the mainstream CMOS know-how, to be able to decrease the actual dimension and the producing fee of the units.
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Extra resources for CMOS High Efficiency On-chip Power Management (Analog Circuits and Signal Processing)
881202 Carlson B, Giolma B (2008) Ti white paper: Smartreflex power and performance management technologies: reduced power consumption, optimized performance. pdf Hattori T, lrita T, Ito M, Yamamoto E, Kato H, Sado G, Yamada Y, Nishiyama K, Yagi H, Koike T, Tsuchihashi Y, Higashida M, Asano H, Hayashibara I, Tatezawa K, Shimazaki Y, Morino N, Hirose K, Tamaki S, Yoshioka S, Tsuchihashi R, Arai N, Akiyama T, Ohno K (2006) A power management scheme controlling 20 power domains for a single-chip mobile processor.
In this book, the two topologies are called low drop-out (LDO) and high drop-out (HDO) respectively. 4), it is obvious that an HDO is less efficient as an LDO. 2 • Stability. NMOS pass element connected in a common-drain (source follower) configuration is a good buffer when driving capacitative loads. The output impedance of an HDO pass element is approximately 1/(gm,N + gmb,N ) instead of ro,P for an LDO, pushing the output pole of the linear regulator to very high frequency. Thus, the linear regulator would always be stable as long as the rest of the circuit (error amplifier) is properly compensated.
For computation-intensive and latency-critical tasks such as video decompression, where short T is critical, raising the clock frequency f can expedite the execution of tasks. For low speed or idle tasks, only a fraction of throughput is required, and completing them ahead of their timing deadline leads to no discernible benefits. Reducing f for these tasks reduces the power consumption, but does not affect the total energy required to complete the task, 2 . Another way of understanding is that even though power which is E = NCVDD consumption is lower, the time required to execute the task becomes longer.